Subjects : digital phase locked loop (DPLL)
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Conference | 2021 | An LUT-based Adaptive DPLL for SSV GNSS Receivers 송영진 International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+) 2021, pp.3360-3367 | 2 | 원문 |
| Journal | 2011 | Low power digital PLL based TDC using low rate clocks Park Mijeong Electronics Letters, v.47, no.14, pp.793-794 | 1 | 원문 |
| Status | Year | Patent Name | Country | Family Pat. | KIPRIS |
|---|---|---|---|---|---|
| Registered | 2013 | DIGITAL PHASE-LOCKED LOOP | UNITED STATES | ||
| Registered | 2016 | 디지털 위상 고정 루프 및 그의 구동방법 | KOREA | KIPRIS |
| Type | Year | Research Project | Primary Investigator | Download |
|---|---|---|---|---|
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