Subjects : Clock scheme
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Journal | 2011 | A 10-bit 30-MS/s Successive Approximation Register Analog-to-Digital Converter for Low-Power Sub-Sampling Applications Cho Young Kyun Microelectronics Journal, v.42, no.12, pp.1335-1342 | 5 | 원문 |
| Conference | 2009 | A 2.85mW 0.12mm2 1.0V 11-bit20-MS/s Algorithmic ADC in 65nm CMOS Nam Jaewon European Solid-State Circuits Conference (ESSCIRC) 2009, pp.468-471 | 6 | 원문 |
| Status | Year | Patent Name | Country | Family Pat. | KIPRIS |
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| Type | Year | Research Project | Primary Investigator | Download |
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