Subjects :
Instruction set architecture
논문 검색결과
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Year |
Title |
Cited |
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Journal
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2024 |
Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes
박진아 IEEE Transactions on Circuits and Systems I: Regular Papers, v.71, no.9, pp.4106-4119 |
8 |
원문
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Journal
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2024 |
Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes
Han Kyuseung IEEE Transactions on Circuits and Systems I: Regular Papers, v.71, no.9, pp.4106-4119 |
8 |
원문
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Journal
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2021 |
Developing a Multicore Platform Utilizing Open RISC-V Cores
Hyeonguk Jang IEEE Access, v.9, pp.120010-120023 |
16 |
원문
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Journal
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2021 |
Developing a Multicore Platform Utilizing Open RISC-V Cores
Han Kyuseung IEEE Access, v.9, pp.120010-120023 |
16 |
원문
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Conference
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2017 |
Implementation of an Asynchronous Micro-Controller on the Commercial FPGA
Zi Ho Shin International Conference on Advanced Computer Theory and Engineering (ICACTE) 2017, pp.1-7 |
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Conference
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2012 |
Analysis of an Asynchronous RISC Processor Based on EISC Instruction Set Architecture
Oh Myeong-Hoon International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2012, pp.1-3 |
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Journal
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2009 |
A Novel Instruction Set for Packet Processing of Network ASIP
정원영 한국통신학회논문지 B : 네트워크 및 서비스, v.34, no.9, pp.939-946 |
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연구보고서 검색결과
| Type |
Year |
Research Project |
Primary Investigator |
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