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Detail
Registered METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME
- Inventors
- Eom Yong Sung, Choi Kwang-Seong, Bae Hyun-Cheol, Moon Jong Tae, 이종현
- Application No.
- 12565171 (2009.09.23)
- Publication No.
- 20100320596 (2010.12.23)
- Registration No.
- 8030200 (2011.10.04)
- Country
- UNITED STATES
- Project Code
- 09MB3700, Wafer Level 3D IC Design and Integration, Choi Kwang-Seong
- Abstract
- A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal with the mixture; and heating the first substrate at a temperature higher than a melting point of the solder particles of the mixture to form a solder layer that covers the at least one of an upper surface and a side surface of the first terminal. The solder particles flow or diffuse toward the terminal in the heated polymer resin to adhere to at least some of the exposed surfaces of the terminal thereby forming the solder layer. The solder layer improves the adhesive strength between the terminals of the semiconductor chip and the substrate in the subsequent flip chip bonding process.