17HB1100, Brain-Inspired Neuromorphic Perception and Learning Processor,
Lee Joo Hyun
Abstract
본 발명은 뉴로모픽 연산 장치에 관한 것이다. 본 발명의 뉴로모픽 연산 장치는 시냅스 회로, 자체적인 커패시턴스 성분을 갖는 메탈 라인, 오실레이터, 비교기, 및 커패시턴스 칼리브레이터를 포함할 수 있다. 시냅스 회로는 PWM 신호와 가중치에 대해 곱연산을 수행하여 전류를 생성하도록 구성될 수 있다. 메탈 라인은 전류에 의한 전하가 저장되는 메탈라인 커패시터를 포함할 수 있다. 오실레이터는 메탈 라인 커패시터에 저장되는 전하에 기초하여 복수의 펄스들을 생성한다. 비교기는 복수의 펄스들의 주파수와 타깃 주파수를 비교하고, 비교 결과에 기초하여 제어 신호를 생성할 수 있다. 커패시턴스 칼리브레이터는 제어 신호에 기초하여, 메탈라인 커패시터의 커패시턴스 값을 조절할 수 있다.
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J. Kim et. al, "Trends in Lightweight Kernel for Many core Based High-Performance Computing", Electronics and Telecommunications Trends. Vol. 32, No. 4, 2017, KOGL Type 4: Source Indication + Commercial Use Prohibition + Change Prohibition
J. Sim et.al, “the Fourth Industrial Revolution and ICT – IDX Strategy for leading the Fourth Industrial Revolution”, ETRI Insight, 2017, KOGL Type 4: Source Indication + Commercial Use Prohibition + Change Prohibition
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