ETRI-Knowledge Sharing Plaform

KOREAN
특허 검색
Status Country
Year ~ Keyword

Detail

Registered SYSTEM-ON-CHIP INCLUDING NETWORK FOR DEBUGGING

Inventors
Han Kyuseung, Jae-Jin Lee, Sukho Lee, Byun Kyung Jin, Kim Sang Pil, Bae Young Hwan
Application No.
16556905 (2019.08.30)
Publication No.
20200092226 (2020.03.19)
Registration No.
11470018 (2022.10.11)
Country
UNITED STATES
Project Code
18HB2600, Development of ultra-low power intelligent edge SoC technology based on lightweight RISC-V processor, Jae-Jin Lee
Abstract
Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.
KSP Keywords
Central controller(CC), Local controller, On-chip, System-On-Chip(SoC), error information
Family
 
패밀리 특허 목록
Status Patent Country KIPRIS
Registered SYSTEM ON CHIP INCLUDING NETWORK FOR DEBUGGING KOREA KIPRIS