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Registered SRAM DEVICE INCLUDING OXIDE SEMICONDUCTOR

Inventors
Jaehyun Moon, Sooji Nam, Cho Sung Haeng, Jae-Eun Pi
Application No.
17529817 (2021.11.18)
Publication No.
20230102625 (2023.03.30)
Registration No.
11895817 (2024.02.06)
Country
UNITED STATES
Project Code
21JB2600, M3D Integrated Device and Architecture Technology Development Based on Low-Temperature Oxide Semiconductor, Cho Sung Haeng
Abstract
Provided is a static random-access memory (SRAM) device. The SRAM device includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes a first NMOS area and a second NMOS area vertically separated from the PMOS area with the first NMOS area therebetween, a first transistor including a first gate electrode disposed on the PMOS area, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, a second transistor including a second gate electrode disposed in the first NMOS area and a second channel vertically overlapping the second gate electrode, and a third transistor including a third gate electrode disposed in the second NMOS area and a third channel vertically overlapping the third gate electrode, wherein the first channel includes silicon, wherein the second channel and the third channel include an oxide semiconductor.
KSP Keywords
Oxide semiconductor, Random Access, Source and drain, Static random-access memory(SRAM), gate electrode, insulating layer
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Status Patent Country KIPRIS
Registered SRAM device including oxide semiconductor KOREA