Subjects :
in-band phase noise
논문 검색결과
| Type |
Year |
Title |
Cited |
Download |
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Journal
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2016 |
A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC
김신웅 IEEE Journal of Solid-State Circuits, v.51, no.2, pp.391-400 |
27 |
원문
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Journal
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2013 |
Consideration on Offset LO Contribution in the Phase Noise of Offset PLL Architecture
Ryu Joon Gyu Microwave and Optical Technology Letters, v.55, no.11, pp.2699-2701 |
1 |
원문
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Journal
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2012 |
A 4-GHz All Digital PLL with Low-Power TDC and Phase-Error Compensation
Lee Ja Yol IEEE Transactions on Circuits and Systems I : Regular Papers, v.59, no.8, pp.1706-1719 |
29 |
원문
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Conference
|
2011 |
A 4-GHz Low-power TDC-based All Digital PLL having 9.6mW and 1.2ps rms jitter
Lee Ja Yol International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals (IMWS-IRFPT) 2011, pp.1-2 |
1 |
원문
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Conference
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2003 |
A low power and low noise frequency synthesizer with a integrated quadrature VCO
Han Seon-Ho Radio Frequency Integrated Circuits Symposium (RFIC) 2003, pp.307-310 |
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원문
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특허 검색결과
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Family Pat. |
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연구보고서 검색결과
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