Subjects : All-digital PLL
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Conference | 2014 | A 230ns settling time type-I PLL with 0.96mW TDC power and simple T<inf>V</inf> calculation algorithm Lee Ja Yol International Midwest Symposium on Circuits and Systems (MWSCAS) 2014, pp.370-373 | 1 | 원문 |
| Journal | 2012 | A 4-GHz All Digital PLL with Low-Power TDC and Phase-Error Compensation Lee Ja Yol IEEE Transactions on Circuits and Systems I : Regular Papers, v.59, no.8, pp.1706-1719 | 29 | 원문 |
| Conference | 2011 | A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation Lee Ja Yol Custom Integrated Circuits Conference (CICC) 2011, pp.1-4 | 6 | 원문 |
| Conference | 2011 | A 4-GHz Low-power TDC-based All Digital PLL having 9.6mW and 1.2ps rms jitter Lee Ja Yol International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals (IMWS-IRFPT) 2011, pp.1-2 | 1 | 원문 |
| Status | Year | Patent Name | Country | Family Pat. | KIPRIS |
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| Type | Year | Research Project | Primary Investigator | Download |
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