Subjects : Silicon process
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Conference | 2022 | M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations Won Jeon International Conference on Artificial Intelligence Circuits and Systems (AICAS) 2022, pp.150-153 | 3 | 원문 |
| Journal | 2010 | Fabrication of Self-Aligned TFTs with a Ultra-Low Temperature Polycrystalline Silicon Process on Metal Foils Jaehyun Moon Solid-State Electronics, v.54, no.11, pp.1326-1331 | 2 | 원문 |
| Journal | 2008 | 3.5-Inch QCIF AMOLED Panels with Ultra-low-Temperature Polycrystalline Silicon Thin Film Transistor on Plastic Substrate Kim Yong Hae ETRI Journal, v.30, no.2, pp.308-314 | 8 | 원문 |
| Conference | 2006 | Self-Aligned Thin Film Transistor Fabrication with an Ultra Low Temperature Polycrystalline Silicon Process on a Benzocyclobutene Planarized Stainless Steel Foil Substrate Jaehyun Moon Materials Research Society (MRS) Meeting 2006 (Spring), pp.1-6 |
| Status | Year | Patent Name | Country | Family Pat. | KIPRIS |
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| Type | Year | Research Project | Primary Investigator | Download |
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