16ZS1200, Near-Zero-Voltage Micro-Grain Architecture for Ultra-Low-Energy Processor,
Jae-Jin Lee
Abstract
<연구 목표> - Sub-threshold 영역에서 안정적인 구동이 가능한 NZV 회로기술 개발 - 미세분할 마이크로그레인 프로세서 아키텍처 개발
<연구 내용> - Sub-threshold 전압 구동 시 트랜지스터들의 동작 특성 분석 - NZV에서 동작 가능한 Logic family 개발 - 프로세서 아키텍처와 합성이 가능한 NZV standard cell library 확보 - NZV-SRAM 개발을 위해 초저전압 구동 SRAM bitcell 설계 - SRAM bitcell layout 토폴로지 연구 - NZV 회로 simulation를 통해 NZV 구동 회로의 온도-딜레이 역전 현상 현상 분석 - Retention voltage, analog dynamic range 분석 - Dynamic power와 leakage power를 최소화 하는 최적 Pipelining 연구 - On-demand voltage scaler 설계를 위한 각 μ-grain간의 Wake-up sequence 연구 및 Supply noise 회피 Power management 구조 연구 - Fine-grain Voltage Scaler 구조 개발
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