17HH3400, 100Gbps Coherent OFDM DSP Development,
Hun Sik Kang
Abstract
[성과 요약] ○ 100G용 Coherent/OFDM DSP 알고리즘 개발 • Coherent/OFDM 변복조/장애요소보상/채널오류정정(LDPC) 개발 • Coherent/OFDM 기반 광전송 신호처리 검증용 시뮬레이터 개발 - Uncoded BER: < 10-3, Coded BER: < 10-12 (기준 SNR=18 dB) - 고정 소수점 처리 구현에 따른 SNR 손실 < 1dB(@ BER = 10-3) • 국내최초 100G용 Coherent/OFDM 기반 광전송 신호처리 기술 확보
○ 100G용 Coherent/OFDM DSP 실시간 처리 구현 • Coherent/OFDM 변복조 및 채널오류 정정(LDPC) 신호처리 HDL 개발 • 100G용 실시간 처리를 위한 정합용 초고속 인터페이스 개발 • 100G용 광전송 실시간 처리를 위한 FPGA 구현 - 송신부(FPGA 1, 점유율 66%), 수신부 (FPGA 4, 점유율: 66%, 51%) • Coherent OFDM 기반 변복조 및 오류정정 통합 시스템 최초 개발
○ 100G용 Coherent/OFDM DSP FPGA 플랫폼 보드 개발 • 100G용 Coherent/OFDM DSP 송신부 FPGA 보드 개발 • 100G용 Coherent/OFDM DSP 수신부 FPGA 보드 개발 • 100G용 Coherent/OFDM DSP 호스트 정합 보드 개발
○ CMOS 공정기반 30GSPS급 초고속 ADC 변환기 IP 개발 • 16채널 sub-ADC로 구성된 Time-Interleaved 방식 ADC 설계 및 제작 • TSMC 40nm CMOS 공정, die 면적: 0.2 mm2 • 소모전력: 115mW, SNDR: 27.98 dB, Figure-of-Merit(FOM): 282 fJ/c-s • 국내 최초 10 GS/s 이상의 초고속 ADC IP 설계 및 제작 기술 확보
○ 100G용 Coherent/OFDM DSP 정합용 광 송수신기 개발 • Dual-Polarization 지원 Coherent 광 송수신기 설계 및 제작 • 30GS/s, 6bits 4채널 DAC/ADC간 정합 연동 확인
○ 100G용 Coherent/OFDM DSP 연동 시험 • Coherent/OFDM 광전송 알고리즘 검증 오프-라인(off-line) 시험 확인 • Coherent OFDM DSP 실시간 구현 송신부 광선로 100km 시험 확인 • Coherent OFDM DSP 실시간 구현 통합 단대단 시험 확인 • Coherent OFDM DSP 실시간 구현 통합 광선로 연동 시험 (공인시험) • 초고속 광전송 시험 및 성능 분석 기술 확보
○ (등록특허) 국제 1, (출원특허) 국내 18, 국제 3 ○ (논문) SCI 논문 5, 국제학회 9, 국내학회 10 ○ (프로그램) 알고리즘 및 실시간처리 구현 프로그램 등록 14건 ○ (개발시제품) FPGA 플랫폼 보드/ADC IP/광 송수신기 등 8건
(출처 : 요약서 8p)
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