Subject

Subjects : Calculation algorithm

  • Articles (6)
  • Patents (1)
  • R&D Reports (0)
논문 검색결과
Type Year Title Cited Download
Conference 2024 A Shipborne Radar Interference Study into 5G Base Stations in the lower 3 GHz band in Korea   Kim Bong-Su  International Conference on Information and Communication Technology Convergence (ICTC) 2024, pp.1419-1420 0 원문
Conference 2014 A 230ns settling time type-I PLL with 0.96mW TDC power and simple T<inf>V</inf> calculation algorithm   Lee Ja Yol  International Midwest Symposium on Circuits and Systems (MWSCAS) 2014, pp.370-373 1 원문
Conference 2012 Work Load Calculation Algorithm for Postal Delivery Operation   Park Jeong-Hyun  International Conference on Future Information Technology (FutureTech) 2012 (LNEE 179), v.179, pp.259-267 0 원문
Conference 2011 A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation   Lee Ja Yol  Custom Integrated Circuits Conference (CICC) 2011, pp.1-4 6 원문
Journal 2011 Low power digital PLL based TDC using low rate clocks   Park Mijeong  Electronics Letters, v.47, no.14, pp.793-794 1 원문
Conference 2001 Real-time implementation of MMSE adaptive beamformer using modified systolic array   Park Jae Joon  Vehicular Technology Conference (VTC) 2001 (Spring), pp.180-184 원문
특허 검색결과
Status Year Patent Name Country Family Pat. KIPRIS
Registered 2006 APPARATUS AND METHOD OF SELECTING LABEL SWITCHED PATH UNITED STATES
연구보고서 검색결과
Type Year Research Project Primary Investigator Download
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