Subject

Subjects : successive approximation register

  • Articles (5)
  • Patents (1)
  • R&D Reports (0)
논문 검색결과
Type Year Title Cited Download
Journal 2012 A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture   Young-Deuk Jeon  IEEE Transactions on Circuits and Systems II : Express Briefs, v.59, no.11, pp.741-745 17 원문
Conference 2012 A 9-bit 100-MS/s Flash-SAR ADC without Track-and-Hold Circuits   Cho Young Kyun  International Symposium on Wireless Communication Systems (ISWCS) 2012, pp.880-884 14 원문
Journal 2011 A 10-bit 30-MS/s Successive Approximation Register Analog-to-Digital Converter for Low-Power Sub-Sampling Applications   Cho Young Kyun  Microelectronics Journal, v.42, no.12, pp.1335-1342 5 원문
Journal 2010 A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique   Cho Young Kyun  IEEE Transactions on Circuits and Systems II : Express Briefs, v.57, no.7, pp.502-506 44 원문
Conference 2010 A 9.15mW 0.22mm<sup>2</sup> 10b 204MS/s pipelined SAR ADC in 65nm CMOS   Young-Deuk Jeon  Custom Integrated Circuits Conference (CICC) 2010, pp.1-4 41 원문
특허 검색결과
Status Year Patent Name Country Family Pat. KIPRIS
Registered 2018 뉴로모픽 연산 장치 및 그것의 동작 방법 KOREA KIPRIS
연구보고서 검색결과
Type Year Research Project Primary Investigator Download
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