Subjects : phase interpolator
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Journal | 2016 | Fractional spur reduction technique using 45° phase dithering in phase interpolator based all‐digital phase‐locked loop 고준수 Electronics Letters, v.52, no.23, pp.1920-1922 | 1 | 원문 |
| Journal | 2008 | A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator 성창경 IEICE Transactions on Communications, v.E91-B, no.5, pp.1397-1402 | 0 | 원문 |
| Conference | 2007 | A New Burst Mode Clock and Data Recovery Circuit Lee Seung-Woo International SoC Design Conference (ISOCC) 2007, pp.215-218 | ||
| Conference | 2006 | Clock and Data Recovery Circuit Using Digital Phase Aligner and Phase Interpolator Lee Seung-Woo Midwest Symposium on Circuits and Systems (MWSCAS) 2006, pp.690-693 | 2 | 원문 |
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| Type | Year | Research Project | Primary Investigator | Download |
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