Subjects : Time-to-Digital Converter
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Journal | 2016 | A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC 김신웅 IEEE Journal of Solid-State Circuits, v.51, no.2, pp.391-400 | 27 | 원문 |
| Journal | 2012 | A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector 최광천 IEEE Transactions on Circuits and Systems II : Express Briefs, v.59, no.3, pp.143-147 | 32 | 원문 |
| Journal | 2011 | Low power digital PLL based TDC using low rate clocks Park Mijeong Electronics Letters, v.47, no.14, pp.793-794 | 1 | 원문 |
| Status | Year | Patent Name | Country | Family Pat. | KIPRIS |
|---|---|---|---|---|---|
| Registered | 2013 | DIGITAL PHASE-LOCKED LOOP | UNITED STATES |
| Type | Year | Research Project | Primary Investigator | Download |
|---|---|---|---|---|
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