Subject

Subjects : Clock and Data Recovery Circuit (CDR)

  • Articles (6)
  • Patents (2)
  • R&D Reports (0)
논문 검색결과
Type Year Title Cited Download
Journal 2013 10-Gbit/s Wireless Communication System at 300 GHz   Tae Jin Chung  ETRI Journal, v.35, no.3, pp.386-396 13 원문
Journal 2008 A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator   성창경  IEICE Transactions on Communications, v.E91-B, no.5, pp.1397-1402 0 원문
Conference 2007 A New Burst Mode Clock and Data Recovery Circuit   Lee Seung-Woo  International SoC Design Conference (ISOCC) 2007, pp.215-218
Conference 2006 Clock and Data Recovery Circuit Using Digital Phase Aligner and Phase Interpolator   Lee Seung-Woo  Midwest Symposium on Circuits and Systems (MWSCAS) 2006, pp.690-693 2 원문
Conference 2006 A 1 .25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution   성창경  International Symposium on Circuits and Systems (ISCAS) 2006, pp.2113-2116 3
Conference 2005 A 1.25Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with an Improved Effective Phase Resolution   성창경  International SoC Design Conference (ISOCC) 2005, pp.247-250
특허 검색결과
Status Year Patent Name Country Family Pat. KIPRIS
Registered 2021 디지털 CDR 회로 및 그것을 포함하는 피드백 루프 회로 KOREA
Registered 2022 DIGITAL CLOCK AND DATA RECOVERY CIRCUIT AND FEEDBACK LOOP CIRCUIT INCLUDING THE SAME UNITED STATES
연구보고서 검색결과
Type Year Research Project Primary Investigator Download
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