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Journal
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2016 |
A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC
김신웅 IEEE Journal of Solid-State Circuits, v.51, no.2, pp.391-400 |
27 |
원문
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Conference
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2009 |
Two-Parallel Concatenated BCH Super-FEC Architecture for 100-GB/S Optical Communications
윤상호 Workshop on Signal Processing Systems (SIPS) 2009, pp.36-39 |
4 |
원문
|
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Conference
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2008 |
100-Gb/s Three-parallel Reed-Solomon Based Foward Error Correction Architecture for Optical Communications
이한호 International SoC Design Conference (ISOCC) 2008, pp.I-265-I-268 |
9 |
원문
|
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Conference
|
2008 |
40-Gb/s Two-Parallel Reed-Solomon based Forward Error Correction Architecture for Optical Communications
이승범 Asia-Pacific Conference on Circuits and Systems (APCCAS) 2008, pp.882-885 |
1 |
원문
|
|
Conference
|
2006 |
Design of Audio and Video Decoder for the T-DMB Receiver
Koo Bon Tae International Conference on Multimedia and Expo (ICME) 2006, pp.1269-1272 |
1 |
원문
|
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Conference
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2006 |
Audio/Video Processing for Single-Chip T-DMB Decoder
Koo Bon Tae International Conference on Consumer Electronics (ICCE) 2006, pp.263-264 |
0 |
원문
|
|
Journal
|
2002 |
A DSP Architecture for High‐Speed FFT in OFDM Systems
Jaesung Lee ETRI Journal, v.24, no.5, pp.391-397 |
13 |
원문
|
|
Journal
|
2002 |
A Design of Low-Power 8-bit Microcontroller
Lee Sangjae 전자공학회논문지 SD, v.39, no.2, pp.63-71 |
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Journal
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2000 |
Design of a High Speed Asymmetric Baseband MODEM ASIC Chip for CATV Network
Park Ki Hyuk 한국통신학회지, v.25, no.9, pp.1332-1339 |
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