Subjects :
Shift Register
논문 검색결과
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2024 |
The High-performance convolution design and implementation using parallel memory processing and shift register pipeline
Youngseok Baek International Conference on Electronics, Information and Communication (ICEIC) 2024, pp.1253-1256 |
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2015 |
New Shift Register Circuit Scheme for Stable Output Using Oxide TFTs
Jae-Eun Pi International Meeting on Information Display (IMID) 2015, pp.334-334 |
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2013 |
High-Speed J-Delayed & K-Dimensional LFSR Architecture in VLSI
Jeong Chan Bok International Midwest Symposium on Circuits and Systems (MWSCAS) 2013, pp.433-436 |
0 |
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Conference
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2011 |
High-Speed Architecture for K-Dimensional LFSR in H/W Implementation
Jeong Chan Bok International Midwest Symposium on Circuits and Systems (MWSCAS) 2011, pp.1-4 |
2 |
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Conference
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2010 |
Design of Parallel Scrambler in High-speed Serial Protocol
Kwon Won-Ok International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2010, pp.59-62 |
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Conference
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2003 |
A fast-serial finite field multiplier without increasing the number of registers
Kim Wonjong International Symposium on Circuits and Systems (ISCAS) 2003, pp.157-160 |
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원문
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Journal
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2002 |
Architecture for decoding adaptive Reed-Solomon codes with variable block length
Mook Kyou Song IEEE Transactions on Consumer Electronics, v.48, no.3, pp.631-637 |
9 |
원문
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Conference
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1988 |
Integrated Parallel Scrambler Design for High-speed Transmission Systems
Sang Hoon Lee International Symposium on Circuits and Systems 1988, pp.361-364 |
1 |
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연구보고서 검색결과
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