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Conference
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2021 |
Active Control and Management System for Providing the Ultra-Low Latency Service on Deterministic Networks
Kim Eung Ha International Conference on Ubiquitous and Future Networks (ICUFN) 2021, pp.70-74 |
3 |
원문
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Journal
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2010 |
Low-Noise Wideband PLL with Dual-Mode Ring-VCO
Lee Hui Dong Electronics Letters, v.46, no.20, pp.1368-1370 |
10 |
원문
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Conference
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2006 |
Low Jitter 1.56GHz PLL Clock Generator for 3.125Gb/s/ch CMOS Serial Link Transceiver
Byun Sangjin International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2006, pp.75-768 |
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Journal
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2006 |
A Gigabit Link CMOS Analog Interface for High Performance Signaling
Sungkyung Park Analog Integrated Circuits and Signal Processing, v.47, no.1, pp.5-12 |
0 |
원문
|
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Journal
|
2005 |
A High-Density Two-Dimensional Parallel Optical Interconnection Module
Han Sang-Pil IEEE Photonics Technology Letters, v.17, no.11, pp.2448-2450 |
19 |
원문
|
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Conference
|
2005 |
A 500MHz DLL with second order duty cycle corrector for low jitter
Kim Dong Kyu Custom Integrated Circuits Conference (CICC) 2005, pp.325-328 |
16 |
원문
|
|
Journal
|
2005 |
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer
김진욱 IEEE Journal of Solid-State Circuits, v.40, no.2, pp.462-471 |
30 |
원문
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