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Journal
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2012 |
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture
Young-Deuk Jeon IEEE Transactions on Circuits and Systems II : Express Briefs, v.59, no.11, pp.741-745 |
17 |
원문
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Journal
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2011 |
A 12-Bit 200-MS/s Pipelined A/D Converter with Sampling skew Reduction Technique
Nam Jaewon Microelectronics Journal, v.42, no.11, pp.1225-1230 |
1 |
원문
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Conference
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2011 |
A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS
Nam Jaewon International SoC Design Conference (ISOCC) 2011, pp.405-407 |
5 |
원문
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Conference
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2008 |
A 159.2mW SoC Implementation of T-DMB Receiver including Stacked Memories
Lee Joo Hyun Custom Integrated Circuits Conference (CICC) 2008, pp.679-682 |
3 |
원문
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Conference
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2007 |
A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS
Young-Deuk Jeon International Solid-State Circuits Conference (ISSCC) 2007, pp.456-615 |
49 |
원문
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