ETRI-Knowledge Sharing Plaform

Analog-To-Digital Converters(ADCs) Distortion Ratio Spurious-Free Dynamic Range(SFDR) Active Area Small Area Capacitor Array High Speed Supply Voltage Successive Approximation Analog-To-Digital Converter(SAR ADC) Cmos Technology Pipelined Adc Chip Area Signal-To-Noise-And-Distortion Sampling Frequency Differential Nonlinearity(DNL) Integral Nonlinearity High Linearity Sampling Rate Heterogeneous Integration Signal Noise Ratio(SNR) Programmable Capacitor 65nm Cmos Micro-Electro-Mechanical System(MEMS) Memristor Device Clock Scheme Flat Panel Display Single-Ended Pre-Emphasis Pipeline Adc Low Power Consumption Flash Adc Successive Approximation Register Analog-To-Digital Converter Figure Of Merit(FoM) Source Follower Reduction Technique Power Reduction Dual-Channel Effective Number Of Bits(ENOB) Variable Gain Amplifier Thin Structure Neuromorphic Hardware Reference Buffer Duty Cycle(DC) Ultra-Thin First Stage A/D Converter Display Applications Mems Microphone Low Drop-Out(LDO) Ldo Regulator Architecture Design Ip-Based Multi-Stage Amplifiers Black-Out Bonding Process Data Transfer Memory Interface Sensor Bias 90-Nm Daisy Chain Design Aspects Fault Detection Scheme Higher Performance Sample-And-Hold Amplifier High-Bandwidth Operational Transconductance Amplifier(OTA) Design Techniques Line-By-Line CAN BUS Complementary Metal-Oxide-Semiconductor(CMOS) Integration Architecture Algorithmic Adc Deep Learning(DL) Current Consumption Single Chip Clamp Circuit Voltage Booster Dynamic Biasing 2.5d Interposers Hardware Accelerator Thermal Stability Hybrid Mac(HMAC) Reference Current Autonomous Driving Reference Generator 45-Nm Cmos Process High Conversion Low-Voltage Circuit Pre-Amplifier Heterogeneous Computing Verification Method Amplifier Sharing Technique Error Correction Learning Algorithm Wheel Speed Sensor Analog Front-End Power Dissipation Bias Voltage Over-Current Protection Hardware Acceleration Area Reduction Open Technology Conversion Rate Die-To-Die Video Applications Level Converter Pipeline Stages Data Explosion Maximum Operating Frequency Operating Speed Scale-Down Target Platform Acquisition Time Autonomous Vehicle Sensor Interface Sub-Adc Readout Integrated Circuit Infrastructure Support Least-Significant Bit(LSB) User Interface(UI) Automotive Systems Offset Calibration Sub-Sampling Image Signal Processing Positive Feedback Low Noise Connection Area Fully Differential Artificial Intelligence Output Voltage Real-Time Processing Digital Calibration Flexible Design Low Power Analog Pipelined Sar Adc Artificial Neural Network Common-Source Circuit Design Semiconductor Technology Common-Mode Voltage(CMV) Driver Circuit Voltage Range Integration Platform Input Signal Output Swing Asynchronous Clock Variation Tolerance Variable Resolution High Resolution Processing Platform Signal Level Sampling Clock Feedback Signal Input Referred Noise Object Recognition Digital-To-Analog Converters Machine Learning Applications Operation Speed 20 Hz Large-Scale Noise Performance Coupling Capacitor Clock Detector Full-Scale High-Density Performance Degradation Switched-Capacitor Circuit Operational Amplifier High-Performance Computing(HPC) Physical Limitation Biasing Technique Technology Infrastructure Amplification Technique Capacitor Switching Distinct Sampling Rejection Ratio Switching Technique Energy-Efficient Lower Cost Pipelined Analog-To-Digital Converter Gain Range Operation Flexibility Signal Amplification Signal Integrity(SI) Digital Signal Multiplying Digital-To-Analog Converter(MDAC) Op-Amp Feedback Coefficient High Power Output Buffer Pvt Variation Decision Feedback Equalizer Noise Filters Flash-Sar Hardware Platform Time Error Cost Efficiency Circuit Complexity Vehicle Control Digital Core Power-Supply Rejection(PSR) Aperture Time Controller Area Network(CAN) Microphone Readout Offset Cancellation Settling Time Area-Efficient 7 Mm