Subject

Subjects : Data recovery circuit

  • Articles (7)
  • Patents (2)
  • R&D Reports (0)
논문 검색결과
Type Year Title Cited Download
Journal 2013 10-Gbit/s Wireless Communication System at 300 GHz   Tae Jin Chung  ETRI Journal, v.35, no.3, pp.386-396 13 원문
Journal 2008 A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator   성창경  IEICE Transactions on Communications, v.E91-B, no.5, pp.1397-1402 0 원문
Conference 2007 A New Burst Mode Clock and Data Recovery Circuit   Lee Seung-Woo  International SoC Design Conference (ISOCC) 2007, pp.215-218
Conference 2006 Clock and Data Recovery Circuit Using Digital Phase Aligner and Phase Interpolator   Lee Seung-Woo  Midwest Symposium on Circuits and Systems (MWSCAS) 2006, pp.690-693 2 원문
Conference 2006 A 1 .25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution   성창경  International Symposium on Circuits and Systems (ISCAS) 2006, pp.2113-2116 3
Conference 2005 A 1.25Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with an Improved Effective Phase Resolution   성창경  International SoC Design Conference (ISOCC) 2005, pp.247-250
Conference 2002 A 0.58-1 Gb/s CMOS data recovery circuit using a synchronous digital phase aligner   Taesik Cheung  Midwest Symposium on Circuits and Systems (MWSCAS) 2002, pp.385-388 원문
특허 검색결과
Status Year Patent Name Country Family Pat. KIPRIS
Registered 2021 통신 시스템에서 응용 서비스 응답 시간 예측 방법 및 장치 KOREA KIPRIS
Registered 2022 METHOD AND APPARATUS FOR PREDICTING APPLICATION SERVICE RESPONSE TIME IN COMMUNICATION SYSTEM UNITED STATES
연구보고서 검색결과
Type Year Research Project Primary Investigator Download
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