Subject

Subjects : High energy efficiency

  • Articles (12)
  • Patents (1)
  • R&D Reports (0)
논문 검색결과
Type Year Title Cited Download
Conference 2023 An Efficient AER Interface Circuit for Scalable Spiking Neural Networks   Kim Sung Eun  International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2023, pp.766-768 0 원문
Journal 2019 Integrated Reconfigurable Silicon Photonics Switch Matrix in IRIS Project: Technological Achievements and Experimental Results   Francesco Testa  IEEE/OSA Journal of Lightwave Technology, v.37, no.2, pp.345-355 23 원문
Journal 2018 An Energy Efficient Charging Technique for Switched Capacitor Voltage Converters With Low-Duty Ratio   Saad Arslan  IEEE Transactions on Circuits and Systems II : Express Briefs, v.65, no.6, pp.779-783 20 원문
Journal 2015 Scalable Application Mapping for SIMD Reconfigurable Architecture   Yongjoo Kim  Journal of Semiconductor Technology and Science, v.15, no.6, pp.634-646 0 원문
Conference 2015 Reliable Continuous Object Tracking with Cost Effectiveness in Wireless Sensor Networks   Seungwoo Hong  International Conference on Ubiquitous and Future Networks (ICUFN) 2015, pp.672-676 8 원문
Journal 2015 Large-Scale Mobile Phenomena Monitoring with Energy-Efficiency in Wireless Sensor Networks   박수창  Computer Networks : The International Journal of Telecommunications Networking, v.81, pp.116-135 26 원문
Journal 2012 Energy-Efficient Boundary Monitoring for Large-Scale Continuous Objects   Seungwoo Hong  IEICE Transactions on Communications, v.E95-B, no.7, pp.2451-2454 1 원문
Journal 2010 SAMAC: A Cross-Layer Communication Protocol for Sensor Networks with Sectored Antennas   Emad Felemban  IEEE Transactions on Mobile Computing, v.9, no.8, pp.1072-1088 42 원문
Journal 2009 Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique   Yang Yil Suk  Journal of Semiconductor Technology and Science, v.9, no.1, pp.1-7
Conference 2008 Design of High Energy Efficiency 32bit Processing Unit Using Instruction-Levels Data Gating and Dynamic Voltage Scaling techniques   Yang Yil Suk  International SoC Design Conference (ISOCC) 2008, pp.II-69-II-72 0 원문
Conference 2008 High Energy Efficient Reconfigurable Processor for Mobile Multimedia   Yeo Soon Il  International Conference on Circuits and Systems for Communications (ICCSC) 2008, pp.618-622 3 원문
Conference 2006 32Bit SIMSD Path Architecture For High Energy Efficiency Using Single/Parallel Mode Bit and 2 Step Gating Technique   Yang Yil Suk  한국반도체 학술 대회 (KCS) 2006, pp.1-2
특허 검색결과
Status Year Patent Name Country Family Pat. KIPRIS
Registered 2006 HIGHLY ENERGY-EFFICIENT PROCESSOR EMPLOYING DYNAMIC VOLTAGE SCALING UNITED STATES
연구보고서 검색결과
Type Year Research Project Primary Investigator Download
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