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Conference
|
2017 |
Silica Filler Content in NCP and its Effects on the Reliability of 3D TSV Multi-Stack under Thermal Shock Test
주니어 Electronics Packaging Technology Conference (EPTC) 2017, pp.1-8 |
8 |
원문
|
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Conference
|
2017 |
Development of Stacking Process for 3D TSV (Through Silicon Via) Structure using Laser
Choi Kwang-Seong International Microelectronics Assembly and Packaging Society (IMAPS) 2017, pp.1-5 |
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원문
|
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Journal
|
2016 |
Characterization of Transmission Lines with Through-silicon-vias and Bump Joints on High-resistivity Si Interposers for RF Three-dimensional Modules
Choi Kwang-Seong Japanese Journal of Applied Physics, v.55, no.6S3, pp.1-5 |
2 |
원문
|
|
Conference
|
2014 |
Fault Detection and Isolation of Multiple Defects in Through Silicon Via (TSV) Channel
정현석 International 3D Systems Integration Conference (3DIC) 2014, pp.1-5 |
5 |
원문
|
|
Conference
|
2014 |
Power Noise Isolation in a Silicon Interposer with Through Silicon Vias
Myunghoi Kim Electronics Packaging Technology Conference (EPTC) 2014, pp.805-808 |
0 |
원문
|
|
Conference
|
2014 |
Sol-gel based metal interconnector improved by carbon nanotubes (CNTs) in through silicon via (TSV) structure
B.M. Sung International Microprocesses and Nanotechnology Conference (MNC) 2014, pp.1-2 |
|
|
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Journal
|
2013 |
Micromachined stress-free TSV hole for AlGaN/GaN-on-Si (1 1 1) platform-based devices
Sang Choon Ko Journal of Micromechanics and Microengineering, v.23, no.3, pp.1-7 |
3 |
원문
|
|
Journal
|
2012 |
Novel Bumping and Underfill Technologies for 3D IC integration
성기준 ETRI Journal, v.34, no.5, pp.706-712 |
31 |
원문
|
|
Conference
|
2012 |
3D SiP Module Using TSV and Novel Low-Volume Solder-on-Pad(SoP) Process
Bae Hyun-Cheol Electronic System-Integration Technology Conference (ESTC) 2012, pp.1-4 |
1 |
원문
|
|
Journal
|
2011 |
Conformal Deposition of an Insulator Layer and Ag Nano Paste Filling of a through Silicon Via for a 3D Interconnection
Baek Kyu-Ha Journal of the Korean Physical Society, v.59, no.3, pp.2252-2258 |
10 |
원문
|
|
Journal
|
2011 |
Dual Etch Processes of Via and Metal Paste Filling for Through Silicon Via Process
함용현 Thin Solid Films, v.519, no.20, pp.6727-6731 |
26 |
원문
|
|
Conference
|
2010 |
Dual Etch Processes of Sloped Via and Paste Fill for Through Silicon Via
Park Kun Sik Asia-Pacific Conference on Plasma Science and Technology (APCPST) 2010 / Symposium on Plasma Science for Materials (SPSM) 2010, pp.1-2 |
|
|
|
Conference
|
2010 |
3D SiP Module using TSV and Novel Solder Bump Maker
Bae Hyun-Cheol Electronic Components and Technology Conference (ECTC) 2010, pp.1637-1641 |
5 |
원문
|