ETRI-Knowledge Sharing Plaform

Phase Noise Real-Time Application Face Detection Virtual Platform Class B Xilinx Virtex Cmos Process Fpga Implementation Negative Resistance Ict Convergence Face Recognition System Continuous Wave Radar Channel Estimation(CE) Eye Detection Estimation Technique Fractional-N Pll Frequency Tuning Range Illumination Invariant Internal Loads Low-Complexity Packet Error Rate Oscillator Circuit Spectrum Leasing Secondary User(Su) Secondary Link Charge Pump High Signal-To-Noise Ratio Haar-Like Features High-Precision Loop Bandwidth Physical Layer Security(Physec) Quality Of Service(QoS) Error Rate Performance Hardware Model Heterogeneous Feature High-Resolution Lc Tank Mimo Detection Multiple Input Multiple Output(MIMO) Optimal Transmission Output Power Rms Error Sub-Mmwave Transmission Strategy 3gpp Lte Systems Channel State Information(CSI) Discrete Cosine Transform Hardware And Software Integrity Verification Modulation Bandwidth Radar Sensing Self-Quotient Image 40nm Cmos Cascaded Classifier Experimental Result Feature Extraction Ka-Band Linear Discriminant Analysis(LDA) Radar Signal Processing Radar System Signal Noise Ratio(SNR) Code Generator Development Environment Differential Vco External And Internal Fmcw Radar Hardware System Illumination Effect Wide Frequency 65nm Cmos Application Software Ergodic Rate High Reliability Imperfect Csit Locking Range Operating System Primary Users(PUs) Push-Pull Qr Decomposition Qos Level Pll Synthesizer Radar Applications Computational Complexity Colpitts Oscillator Detection Techniques Detection Algorithm Hardware Implementation High Speed Lte Downlink M-Algorithm Quasi-Ml Secrecy Rate Transmit Beamforming Transaction Level Model Verification Module Wide Tuning Hw-Sw Codesign 5 Ghz