Subject

Subjects : Data recovery

  • Articles (13)
  • Patents (3)
  • R&D Reports (0)
논문 검색결과
Type Year Title Cited Download
Journal 2024 Alamouti-coded DSP algorithm with a simplified PTBC decoder for next-generation optical access networks   Oh Jung-Yeol  Optics Express, v.32, no.11, pp.18727-18741 2 원문
Journal 2022 A 0.9‐V human body communication receiver using a dummy electrode and clock phase inversion scheme   Oh Kwang Il  ETRI Journal, v.44, no.5, pp.859-874 1 원문
Journal 2020 Experimental Demonstration of a Photonic Frame Based Packet-Switched Optical Network for Data Centers   Yongwook Ra  IEEE/OSA Journal of Lightwave Technology, v.38, no.6, pp.1113-1124 7 원문
Journal 2013 10-Gbit/s Wireless Communication System at 300 GHz   Tae Jin Chung  ETRI Journal, v.35, no.3, pp.386-396 13 원문
Journal 2008 A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator   성창경  IEICE Transactions on Communications, v.E91-B, no.5, pp.1397-1402 0 원문
Journal 2008 A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits   박현  ETRI Journal, v.30, no.2, pp.275-281 0 원문
Conference 2007 A Novel Pulse That Jointly Optimizes Symbol Timing Estimation and Mean Squared Error in Data Recovery   Lee Seung Joon  Global Telecommunications Conference (GLOBECOM) 2007, pp.4035-4039 1 원문
Conference 2007 A New Burst Mode Clock and Data Recovery Circuit   Lee Seung-Woo  International SoC Design Conference (ISOCC) 2007, pp.215-218
Conference 2006 Clock and Data Recovery Circuit Using Digital Phase Aligner and Phase Interpolator   Lee Seung-Woo  Midwest Symposium on Circuits and Systems (MWSCAS) 2006, pp.690-693 2 원문
Conference 2006 A 1 .25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution   성창경  International Symposium on Circuits and Systems (ISCAS) 2006, pp.2113-2116 3
Conference 2005 A 1.25Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with an Improved Effective Phase Resolution   성창경  International SoC Design Conference (ISOCC) 2005, pp.247-250
Journal 2005 A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer   김진욱  IEEE Journal of Solid-State Circuits, v.40, no.2, pp.462-471 30 원문
Conference 2002 A 0.58-1 Gb/s CMOS data recovery circuit using a synchronous digital phase aligner   Taesik Cheung  Midwest Symposium on Circuits and Systems (MWSCAS) 2002, pp.385-388 원문
특허 검색결과
Status Year Patent Name Country Family Pat. KIPRIS
Registered 2021 디지털 CDR 회로 및 그것을 포함하는 피드백 루프 회로 KOREA
Registered 2022 DIGITAL CLOCK AND DATA RECOVERY CIRCUIT AND FEEDBACK LOOP CIRCUIT INCLUDING THE SAME UNITED STATES
Registered 2005 CLOCK AND DATA RECOVERY APPARATUS UNITED STATES
연구보고서 검색결과
Type Year Research Project Primary Investigator Download
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