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Conference
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2022 |
Releasing the Memory Bottleneck to Display Video Correctly
Hyeonguk Jang International SoC Design Conference (ISOCC) 2022, pp.340-341 |
0 |
원문
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Conference
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2022 |
Roofline model and Profiling of HPC benchmarks
Eo Ik Soo International Conference on Electronics, Information and Communication (ICEIC) 2022, pp.1-4 |
2 |
원문
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Conference
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2021 |
Performance Evaluation on Optically Disaggregated Memory Architecture
Jongtae Song International Conference on Information and Communication Technology Convergence (ICTC) 2021, pp.637-639 |
0 |
원문
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Conference
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2020 |
Implementation and Analysis of a Memory-semantic Interconnect based on Gen-Z Protocol
Seok Bin Hong International Conference on Consumer Electronics (ICCE) 2020 : Asia, pp.400-403 |
2 |
원문
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Journal
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2020 |
40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D
Han Jin Ho ETRI Journal, v.42, no.4, pp.468-479 |
11 |
원문
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Conference
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2018 |
Memory controller structure and design of Visual Intelligence Chip
Kim Byung Jo 대한전자공학회 학술 대회 (추계) 2018, pp.171-174 |
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Conference
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2016 |
An Efficient Motion Estimation Hardware Architecture using Modified Reference Data Access(MRDAS) Skip Algorithm for High Efficiency Video Coding(HEVC) Encoder
Park Seong Mo International Conference on Consumer Electronics (ICCE) 2016 : Berlin, pp.88-92 |
5 |
원문
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Conference
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2015 |
A Hybrid Embedded Compression Codec Engine for Ultra HD Video Application
Park Seong Mo International Conference on Very Large Scale Integration (VLSI-SoC) 2015, pp.292-296 |
1 |
원문
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Conference
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2014 |
The Memory Bandwidth Efficient CTU-Aligned DV Derivation in 3D-HEVC
Bang-Gun International Conference on 3D Systems and Applications (3DSA) 2014, pp.1-3 |
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Conference
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2011 |
A 166.7 Mhz 1920×1080 60fps H.264/SVC Video Decoder
Cho Seunghyun International SoC Design Conference (ISOCC) 2011, pp.278-281 |
0 |
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Journal
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2011 |
Memory and Computation Efficient Hardware Design for a 3 Spatial and Temporal Layers SVC Encoder
이규중 IEEE Transactions on Consumer Electronics, v.57, no.4, pp.1921-1928 |
1 |
원문
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Conference
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2011 |
Memory Efficient Hardware Design for a 3-Spatial Layer SVC Encoder
이규종 International Midwest Symposium on Circuits and Systems (MWSCAS) 2011, pp.1-4 |
0 |
원문
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Journal
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2010 |
Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA-Embedded Instruction-Set Processor
Kwon Young-Su Journal of Circuits, Systems and Computers, v.19, no.7, pp.1435-1447 |
0 |
원문
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Journal
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2010 |
Partial Access Conflict-Relieving Programmable Address Shuffler for Parallel Memory System in Multi-Core Processor
Kwon Young-Su Microprocessors and Microsystems, v.34, no.1, pp.1-13 |
2 |
원문
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Conference
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2009 |
Partial Conflict-Relieving Programmable Address Shuffler for Parallel Memories in Multi-Core Processor
Kwon Young-Su Asia and South Pacific Design Automation Conference (ASP-DAC) 2009, pp.329-334 |
2 |
원문
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Conference
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2008 |
Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA-Embedded Instruction-Set Processor
Kwon Young-Su International Conference on Field Programmable Logic and Applications (FPL) 2008, pp.209-214 |
0 |
원문
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Journal
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2001 |
A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system
박용하 IEEE Journal of Solid-State Circuits, v.36, no.6, pp.944-955 |
18 |
원문
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